TESTER WITH ACCELERATION FOR PACKET BUILDING WITHIN A FPGA BLOCK

A method for testing using an automated test equipment is presented. The method comprises transmitting instructions for performing an automated test from a system controller to a tester processor, wherein the instructions comprise parameters for a descriptor module. The method also comprises programming a reconfigurable circuit for implementing the descriptor module onto an instantiated FPGA block coupled to the tester processor. Further, the method comprises interpreting the parameters from the descriptor module using the reconfigurable circuit, wherein the parameters control execution of a plurality of test operations on a DUT coupled to the instantiated FPGA block. Additionally, the method comprises constructing at least one packet in accordance with the parameters, wherein each one of the at least one packet comprises a command for executing a test operation on the DUT. Finally, the method comprises performing a handshake with the DUT to route the at least one packet to the DUT.