Memory Architecture for Layered Low-Density Parity-Check Decoder

Memory Architecture for Layered Low-Density Parity-Check Decoder

A LE hard decision memory comprises a global mapping element to interleave L values from a first and second circulant and store the interleaved values in a first memory element. A low-density parity-check decoder then processes the circulants from the first memory element and stores output in a seco...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: HAN YANG, ZHANG KAICHI, WANG CHUNG-LI, LI ZONGWANG
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A LE hard decision memory comprises a global mapping element to interleave L values from a first and second circulant and store the interleaved values in a first memory element. A low-density parity-check decoder then processes the circulants from the first memory element and stores output in a second memory element. The LE hard decision memory does not include any mux-demux elements.