3D ASSEMBLY FOR INTERPOSER BOW

3D ASSEMBLY FOR INTERPOSER BOW

A method for packaging a semiconductor device includes attaching a first array of solder material to a first surface of an interposer; bringing the first array of solder material into physical contact with a laminate; and initially bonding the interposer to the laminate by applying a first temperatu...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: SAKUMA KATSUYUKI, INTERRANTE MARIO J
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A method for packaging a semiconductor device includes attaching a first array of solder material to a first surface of an interposer; bringing the first array of solder material into physical contact with a laminate; and initially bonding the interposer to the laminate by applying a first temperature and pressure gradient to the first array of solder material such that a melting temperature of the first array of solder material is not exceeded.