WELL-BIASING CIRCUIT FOR INTEGRATED CIRCUIT

WELL-BIASING CIRCUIT FOR INTEGRATED CIRCUIT

A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is...

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Hauptverfasser: THAKUR NISHANT SINGH, SINHA SAMAKSH, RANA MANMOHAN
Format: Patent
Sprache:eng
Schlagworte:
CONTROLLING
PHYSICS
REGULATING
SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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creator THAKUR NISHANT SINGH
SINHA SAMAKSH
RANA MANMOHAN
description A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2014197883A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2014197883A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2014197883A13</originalsourceid><addsrcrecordid>eNrjZNAOd_Xx0XXydAz29HNXcPYMcg71DFFw8w9S8PQLcXUPcgxxdYEJ8zCwpiXmFKfyQmluBmU31xBnD93Ugvz41OKCxOTUvNSS-NBgIwNDE0NLcwsLY0dDY-JUAQAIuyXu</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>WELL-BIASING CIRCUIT FOR INTEGRATED CIRCUIT</title><source>esp@cenet</source><creator>THAKUR NISHANT SINGH ; SINHA SAMAKSH ; RANA MANMOHAN</creator><creatorcontrib>THAKUR NISHANT SINGH ; SINHA SAMAKSH ; RANA MANMOHAN</creatorcontrib><description>A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively.</description><language>eng</language><subject>CONTROLLING ; PHYSICS ; REGULATING ; SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES</subject><creationdate>2014</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20140717&amp;DB=EPODOC&amp;CC=US&amp;NR=2014197883A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20140717&amp;DB=EPODOC&amp;CC=US&amp;NR=2014197883A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>THAKUR NISHANT SINGH</creatorcontrib><creatorcontrib>SINHA SAMAKSH</creatorcontrib><creatorcontrib>RANA MANMOHAN</creatorcontrib><title>WELL-BIASING CIRCUIT FOR INTEGRATED CIRCUIT</title><description>A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively.</description><subject>CONTROLLING</subject><subject>PHYSICS</subject><subject>REGULATING</subject><subject>SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2014</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAOd_Xx0XXydAz29HNXcPYMcg71DFFw8w9S8PQLcXUPcgxxdYEJ8zCwpiXmFKfyQmluBmU31xBnD93Ugvz41OKCxOTUvNSS-NBgIwNDE0NLcwsLY0dDY-JUAQAIuyXu</recordid><startdate>20140717</startdate><enddate>20140717</enddate><creator>THAKUR NISHANT SINGH</creator><creator>SINHA SAMAKSH</creator><creator>RANA MANMOHAN</creator><scope>EVB</scope></search><sort><creationdate>20140717</creationdate><title>WELL-BIASING CIRCUIT FOR INTEGRATED CIRCUIT</title><author>THAKUR NISHANT SINGH ; SINHA SAMAKSH ; RANA MANMOHAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2014197883A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2014</creationdate><topic>CONTROLLING</topic><topic>PHYSICS</topic><topic>REGULATING</topic><topic>SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES</topic><toplevel>online_resources</toplevel><creatorcontrib>THAKUR NISHANT SINGH</creatorcontrib><creatorcontrib>SINHA SAMAKSH</creatorcontrib><creatorcontrib>RANA MANMOHAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>THAKUR NISHANT SINGH</au><au>SINHA SAMAKSH</au><au>RANA MANMOHAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>WELL-BIASING CIRCUIT FOR INTEGRATED CIRCUIT</title><date>2014-07-17</date><risdate>2014</risdate><abstract>A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively.</abstract><oa>free_for_read</oa></addata></record>
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subjects CONTROLLING
PHYSICS
REGULATING
SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
title WELL-BIASING CIRCUIT FOR INTEGRATED CIRCUIT
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-09T19%3A32%3A35IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=THAKUR%20NISHANT%20SINGH&rft.date=2014-07-17&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2014197883A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true