WELL-BIASING CIRCUIT FOR INTEGRATED CIRCUIT

A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively.