LOW-COST LOW-PROFILE SOLDER BUMP PROCESS FOR ENABLING ULTRA-THIN WAFER-LEVEL PACKAGING (WLP) PACKAGES

LOW-COST LOW-PROFILE SOLDER BUMP PROCESS FOR ENABLING ULTRA-THIN WAFER-LEVEL PACKAGING (WLP) PACKAGES

Techniques are described herein for a dip soldering process which provides a low-profile, low-cost solder bump formation process which may be implemented to promote package thickness scaling (e.g., reduce the overall package thickness). For example, the dip soldering process disclosed herein may ena...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: ZHOU TIAO, THAMBIDURAI KARTHIK, KHANDEKAR VIREN
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:Techniques are described herein for a dip soldering process which provides a low-profile, low-cost solder bump formation process which may be implemented to promote package thickness scaling (e.g., reduce the overall package thickness). For example, the dip soldering process disclosed herein may enable ultra-thin wafer-level packages (WLP), ultra-thin wafer level quad-flat no-leads (WQFN) packages, or the like.