Read Assist Scheme for Reducing Read Access Time in a Memory

A read circuit includes a precharge circuit, coupled with at least a subset of bit lines and a sense circuit in a memory, and a transmission gate. The precharge circuit receives a first control signal and is operative during a first mode to set the bit lines to a first voltage level and to set an input to the sense circuit to a second voltage level. The transmission gate connects a given one of the bit lines with the sense circuit during a second mode as a function of a second control signal, such that when reading a first logic level from the selected memory cell, when the input of the sense circuit is connected with the given bit line, the given bit line is discharged to at least a third voltage, which is between the first and second voltage levels, thereby reducing a read access time in the memory.