High-Performance Scalable Read-Only-Memory Cell

A two-bit read-only-memory (ROM) cell and method of sensing its data state. Each ROM cell in an array includes a single n-channel metal-oxide-semiconductor (MOS) transistor with a source biased to a reference voltage, and its drain connected by a contact or via to one or none of first, second, and third bit lines associated with its column in the array. Each row in the array is associated with a word line serving as the transistor gates for the cells in that row. In response to a column address, a column select circuit selects one pair of the three bit lines to be applied to a sense line in wired-NOR fashion for sensing.