PARALLEL PROCESSING OF MULTIPLE BLOCK COHERENCE OPERATIONS

A method to eliminate the delay of multiple overlapping block invalidate operations in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. The cache controller performing the block invalidate operation merges multiple ove...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	BHORIA NAVEEN, DAMODARAN RAGURAM
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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