PARALLEL PROCESSING OF MULTIPLE BLOCK COHERENCE OPERATIONS

A method to eliminate the delay of multiple overlapping block invalidate operations in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. The cache controller performing the block invalidate operation merges multiple ove...

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Bibliographische Detailangaben
Hauptverfasser: BHORIA NAVEEN, DAMODARAN RAGURAM
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A method to eliminate the delay of multiple overlapping block invalidate operations in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. The cache controller performing the block invalidate operation merges multiple overlapping requests into a parallel stream to eliminate execution delays. Cache operations other that block invalidate, such as block write back or block write back invalidate may also be merged into the execution stream.