SRAM WITH IMPROVED WRITE OPERATION

A memory including an array of memory cells, word lines, and voltage supply lines. Each voltage supply line of the plurality of voltage supply lines is coupled to a first voltage supply terminal of a subset of memory cells of subsets of memory cells of the array. Each memory cell of the array is coupled to a word line. The memory includes a row decoder that controls a voltage on each of the word lines and controls a voltage on each of the voltage supply lines. The row decoder provides a low voltage state voltage on one of the voltage supply lines during a write operation to a subset of memory cells coupled to the voltage supply line and the row decoder provides a high voltage state voltage to the voltage supply line during a read operation of the subset of the memory cells.