REFERENCE VOLTAGE GENERATION CIRCUIT

A reference voltage generation circuit includes a standard electrical current path including at least a pair of NMOS and PMOS, and a constant electrical current supplying circuit for supplying a constant electrical current to the standard electrical current path. The pair of NMOS and PMOS is configured to share a gate potential and a source-drain electrical current. Accordingly, the reference voltage generation circuit is configured to generate a reference voltage as a potential difference between two positions sandwiching the NMOS and PMOS. The reference voltage generation circuit further includes a timing compensation circuit. The timing compensation circuit includes a compensation DMOS for forming a detour electrical current path for bypassing the NMOS according to an on signal.