STRESS-REDUCED CIRCUIT BOARD AND METHOD FOR FORMING THE SAME

A stress-reduced circuit board includes an insulating substrate, and first and second electrically conductive layers which are stacked one upon the other, and which respectively have peripheral marginal regions that are configured in a stepped arrangement. The first electrically conductive layer is...

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Bibliographische Detailangaben
Hauptverfasser: WEI CHIENNG, CHENG WU-HUI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A stress-reduced circuit board includes an insulating substrate, and first and second electrically conductive layers which are stacked one upon the other, and which respectively have peripheral marginal regions that are configured in a stepped arrangement. The first electrically conductive layer is configured to have an area dimension larger than that of the second electrically conductive layer and a thickness not greater than that of the second electrically conductive layer so as to minimize stress caused by a difference in coefficients of thermal expansion between the insulating substrate and the first and second electrically conductive layers.