INFORMATION PROCESSING DEVICE AND BARRIER SYNCHRONIZATION METHOD

An information processing device includes a plurality of barrier banks, and one or more processors including at least one of the plurality of barrier banks. Each of barrier banks includes one or more hardware threads and a barrier synchronization mechanism. The barrier synchronization mechanism includes a bottom unit having a barrier state, and a bitmap indicating that each of the one or more hardware threads has arrived at a synchronization point, and a top unit having a non-arrival counter indicating the number of barrier banks yet to be synchronized. The bottom unit notifies of bottom unit synchronization completion when all the one or more hardware threads have arrived at a barrier synchronization point. The non-arrival counter decrements its value by 1 upon receipt of the bottom unit synchronization completion, and the top unit sets the barrier state to a value indicating synchronization completion when the non-arrival counter decrements to 0.