THERMAL MANAGEMENT FLOORPLAN FOR A MULTI-TIER STACKED IC PACKAGE

THERMAL MANAGEMENT FLOORPLAN FOR A MULTI-TIER STACKED IC PACKAGE

A first tier die is provided having a thermal management floorplan with a heat region having an area for thermal coupling to a heat sink, a second tier die is provided, shaped and dimensioned to be stackable into a multi-tier stack with the first tier die and, when stacked in the multi-tier stack, t...

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Bibliographische Detailangaben
Hauptverfasser: RAKOJCIC RATIBOR, CHIRIAC VICTOR A, LISK DURODAMI J
Format: Patent
Sprache:eng
Schlagworte:
CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
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Beschreibung
Zusammenfassung:A first tier die is provided having a thermal management floorplan with a heat region having an area for thermal coupling to a heat sink, a second tier die is provided, shaped and dimensioned to be stackable into a multi-tier stack with the first tier die and, when stacked in the multi-tier stack, to not substantially overlap the heat region. A heat sink is provided, and a thermal coupling element, the heat sink, a stack having the first tier die and the second tier die, and the heat sink are arranged to form the multi-tier stacked integrated circuit. In the arrangement, the thermal coupling element is located to form a thermal path from the heat region of the first tier die to the heat sink.