Input Output Bridging

In one embodiment, a system includes a memory and a first bridge unit for processor access with the memory coupled with an input-output bus and the memory. The first bridge unit is configured to receive requests from the input-output bus to read or write data receive requests from the MFNU to free memory and choose among the requests to send to the memory on a first memory bus. The system also includes a second bridge unit for packet data access with the memory coupled with a packet input unit, packet output unit, and the memory. The second bridge unit is configured to receive requests to write packet data from the packet input unit, receive requests to read packet data from the packet output unit, and choose among the requests from the packet input unit and the packet output unit to send to the memory on a second memory bus.