IMPEDANCE OPTIMIZED CHIP SYSTEM
A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package...
Gespeichert in:
| Hauptverfasser: | , , , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | ROOZEBOOM DOMINICUS MARINUS NUNN WAYNE A SPEHAR JAMES RAYMOND PAQUET CHRISTIAN SCHULZE JOSEPH KHALSA FATHA |
| description | A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2013268909A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2013268909A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2013268909A13</originalsourceid><addsrcrecordid>eNrjZJD39A1wdXH0c3ZV8A8I8fT1jHJ1UXD28AxQCI4MDnH15WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgaGxkZmFpYGlo6GxsSpAgBh1CKu</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>IMPEDANCE OPTIMIZED CHIP SYSTEM</title><source>esp@cenet</source><creator>ROOZEBOOM DOMINICUS MARINUS ; NUNN WAYNE A ; SPEHAR JAMES RAYMOND ; PAQUET CHRISTIAN ; SCHULZE JOSEPH ; KHALSA FATHA</creator><creatorcontrib>ROOZEBOOM DOMINICUS MARINUS ; NUNN WAYNE A ; SPEHAR JAMES RAYMOND ; PAQUET CHRISTIAN ; SCHULZE JOSEPH ; KHALSA FATHA</creatorcontrib><description>A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20131010&DB=EPODOC&CC=US&NR=2013268909A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20131010&DB=EPODOC&CC=US&NR=2013268909A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ROOZEBOOM DOMINICUS MARINUS</creatorcontrib><creatorcontrib>NUNN WAYNE A</creatorcontrib><creatorcontrib>SPEHAR JAMES RAYMOND</creatorcontrib><creatorcontrib>PAQUET CHRISTIAN</creatorcontrib><creatorcontrib>SCHULZE JOSEPH</creatorcontrib><creatorcontrib>KHALSA FATHA</creatorcontrib><title>IMPEDANCE OPTIMIZED CHIP SYSTEM</title><description>A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJD39A1wdXH0c3ZV8A8I8fT1jHJ1UXD28AxQCI4MDnH15WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgaGxkZmFpYGlo6GxsSpAgBh1CKu</recordid><startdate>20131010</startdate><enddate>20131010</enddate><creator>ROOZEBOOM DOMINICUS MARINUS</creator><creator>NUNN WAYNE A</creator><creator>SPEHAR JAMES RAYMOND</creator><creator>PAQUET CHRISTIAN</creator><creator>SCHULZE JOSEPH</creator><creator>KHALSA FATHA</creator><scope>EVB</scope></search><sort><creationdate>20131010</creationdate><title>IMPEDANCE OPTIMIZED CHIP SYSTEM</title><author>ROOZEBOOM DOMINICUS MARINUS ; NUNN WAYNE A ; SPEHAR JAMES RAYMOND ; PAQUET CHRISTIAN ; SCHULZE JOSEPH ; KHALSA FATHA</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2013268909A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>ROOZEBOOM DOMINICUS MARINUS</creatorcontrib><creatorcontrib>NUNN WAYNE A</creatorcontrib><creatorcontrib>SPEHAR JAMES RAYMOND</creatorcontrib><creatorcontrib>PAQUET CHRISTIAN</creatorcontrib><creatorcontrib>SCHULZE JOSEPH</creatorcontrib><creatorcontrib>KHALSA FATHA</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ROOZEBOOM DOMINICUS MARINUS</au><au>NUNN WAYNE A</au><au>SPEHAR JAMES RAYMOND</au><au>PAQUET CHRISTIAN</au><au>SCHULZE JOSEPH</au><au>KHALSA FATHA</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>IMPEDANCE OPTIMIZED CHIP SYSTEM</title><date>2013-10-10</date><risdate>2013</risdate><abstract>A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US2013268909A1 |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | IMPEDANCE OPTIMIZED CHIP SYSTEM |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T19%3A48%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=ROOZEBOOM%20DOMINICUS%20MARINUS&rft.date=2013-10-10&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2013268909A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |