IMPEDANCE OPTIMIZED CHIP SYSTEM

A high bandwidth circuit is segmented into a plurality of portions, each portion for implementation on a corresponding semiconductor chip, an arrangement of one or more die bond pads for each corresponding chip is generated, and a chip location for each corresponding chip is generated, given package and given package I/O arrangement is generated, the generation of the die bond arrangements and the chip position being relative to given chip package parameters, and being generated to establish bond wire lengths meeting given characteristic impedance parameters. Boundary parameters for generating the segmenting are provided, including a bound on the number of portions and optionally a including bound on the area parameters of the corresponding semiconductor chips.