STABILITY CORRECTION FOR A SHUFFLER OF A SIGMA-DELTA ADC

A sigma-delta analog-to-digital converter ("SigmaDelta ADC") may include a loop filter, ADC, a feedback digital-to-analog converter ("DAC"), and a control circuit. The feedback DAC may include several unit elements (resistors, capacitors, or current sources) that, ideally, are identical to each other but vary due to mismatch errors introduced during manufacture. Mismatch errors may introduce signal errors that generate undesirable noise frequencies and non-linearities in a SigmaDelta ADC output signal. Embodiments of the present invention provide a stability corrected second order shuffler that allows for the shaping of the frequency response by the SigmaDelta ADC to reduce the effect of the mismatch error between DAC unit elements. The second order shuffler may include accumulation correctors, to suppress saturation for accumulators within the shuffler. The suppression may compress the range of accumulation values for each accumulator while maintaining context for the values to stabilize operation of the second order shuffler.