Delay Lock Loop Circuit and Method

A delay lock loop circuit includes a voltage controlled delay line for generating a plurality of specific phase differential signals and a feedback signal according to an input clock source and a control voltage, a detector for comparing at least one of phases and frequencies of the input clock source and the feedback signal to generate at least one detection signal, a charge pump for generating the control voltage according to the at least one detection signal, and a phase selection buffer for generating the output clock source according to the plurality of specific phase differential signals, wherein each of the plurality of specific phase differential signals includes at least a non-inversion signal and an inversion signal, and the feedback signal is the inversion signal of one of the plurality of specific phase differential signals.