Content-Addressable Memory Architecture for Routing Raw Hit Lines Using Minimal Base Metal Layers

A CAM circuit includes a plurality of core memory cells, each cell including comparison logic for generating a local match signal based on a comparison between stored data in the cell and a compare value. The CAM circuit includes a plurality of local match lines, each local match line coupled with a corresponding cell and adapted to convey the local match signal generated by the cell. The CAM circuit includes combination logic for receiving respective local match signals generated by a subset of the cells and for generating an output word match signal having a value indicative of the local match signals. The subset of cells is arranged with at least one block having a word size that is limited based on available space for routing tracks used to convey the local match signals and at least one word match signal in a base metal layer across the cells.