METHOD AND APPARATUS FOR TRANSITIONING A SYSTEM TO AN ACTIVE DISCONNECT STATE

METHOD AND APPARATUS FOR TRANSITIONING A SYSTEM TO AN ACTIVE DISCONNECT STATE

A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.

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Bibliographische Detailangaben
Hauptverfasser: FRY WALTER G, ZHENG XIAOGANG, SO MING L, DURAN FRANCISCO L, BRANOVER ALEXANDER J, STEINMAN MAURICE B, LUECK ANDREW W, SMITH LAURA M, SHIMIZU DAN P, BERNUCHO KRISHNA S, BLINZER PAUL, SIMPSON GARY H, NG MOM-ENG, IBRAHIM ALI
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.