VOID FREE INTERLAYER DIELECTRIC
A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further inc...
Gespeichert in:
Hauptverfasser: | , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | NGO MINH VAN HUI ANGELA T TOKUNO HIROKAZU LI WENMEI THIO HSIAO-HAN |
description | A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2013140720A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2013140720A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2013140720A13</originalsourceid><addsrcrecordid>eNrjZJAP8_d0UXALcnVV8PQLcQ3ycYx0DVJw8XT1cXUOCfJ05mFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgaGxoYmBuZGBo6GxsSpAgBTLiJt</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>VOID FREE INTERLAYER DIELECTRIC</title><source>esp@cenet</source><creator>NGO MINH VAN ; HUI ANGELA T ; TOKUNO HIROKAZU ; LI WENMEI ; THIO HSIAO-HAN</creator><creatorcontrib>NGO MINH VAN ; HUI ANGELA T ; TOKUNO HIROKAZU ; LI WENMEI ; THIO HSIAO-HAN</creatorcontrib><description>A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130606&DB=EPODOC&CC=US&NR=2013140720A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25568,76551</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130606&DB=EPODOC&CC=US&NR=2013140720A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NGO MINH VAN</creatorcontrib><creatorcontrib>HUI ANGELA T</creatorcontrib><creatorcontrib>TOKUNO HIROKAZU</creatorcontrib><creatorcontrib>LI WENMEI</creatorcontrib><creatorcontrib>THIO HSIAO-HAN</creatorcontrib><title>VOID FREE INTERLAYER DIELECTRIC</title><description>A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJAP8_d0UXALcnVV8PQLcQ3ycYx0DVJw8XT1cXUOCfJ05mFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgaGxoYmBuZGBo6GxsSpAgBTLiJt</recordid><startdate>20130606</startdate><enddate>20130606</enddate><creator>NGO MINH VAN</creator><creator>HUI ANGELA T</creator><creator>TOKUNO HIROKAZU</creator><creator>LI WENMEI</creator><creator>THIO HSIAO-HAN</creator><scope>EVB</scope></search><sort><creationdate>20130606</creationdate><title>VOID FREE INTERLAYER DIELECTRIC</title><author>NGO MINH VAN ; HUI ANGELA T ; TOKUNO HIROKAZU ; LI WENMEI ; THIO HSIAO-HAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2013140720A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>NGO MINH VAN</creatorcontrib><creatorcontrib>HUI ANGELA T</creatorcontrib><creatorcontrib>TOKUNO HIROKAZU</creatorcontrib><creatorcontrib>LI WENMEI</creatorcontrib><creatorcontrib>THIO HSIAO-HAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NGO MINH VAN</au><au>HUI ANGELA T</au><au>TOKUNO HIROKAZU</au><au>LI WENMEI</au><au>THIO HSIAO-HAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>VOID FREE INTERLAYER DIELECTRIC</title><date>2013-06-06</date><risdate>2013</risdate><abstract>A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US2013140720A1 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | VOID FREE INTERLAYER DIELECTRIC |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-16T13%3A51%3A13IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=NGO%20MINH%20VAN&rft.date=2013-06-06&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2013140720A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |