INTERLEAVING ADDRESS MODIFICATION

An apparatus having a plurality of memory blocks and a circuit is disclosed. The circuit may be configured to (i) generate a second address by removing one or more first bits of a first address from one or more first locations defined by a first value, (ii) generate a third address by adding an offset value to the second address and (iii) generate a fourth address by inserting a selected one of a plurality of modifiers into the third address. The selected modifier may be inserted into the third address at the first locations. Each modifier is generally associated with a respective one of a plurality of buffers formed in the memory blocks. The circuit may also be configured to access the respective buffer of the fourth address.