SIMULATED NVRAM

SIMULATED NVRAM

Embodiments of the invention relate to leveraging disk controller cache memory to simulate non-volatile random access memory. At least one logical block address in cache memory of the disk controller is designated and set aside as permanently dirty. Read operations may be supported with data in the...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: BROSNAN SUSAN W, LANDERS, JR. JOHN DAVID, HOGAN PATRICIA S, STEINER DAVID J
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:Embodiments of the invention relate to leveraging disk controller cache memory to simulate non-volatile random access memory. At least one logical block address in cache memory of the disk controller is designated and set aside as permanently dirty. Read operations may be supported with data in the cache memory; including data retained in any block address designated as permanently dirty. Write operations may also be supported by storing the write data in the logical block address designated as permanently dirty.