POWER-SAVING RECEIVER CIRCUITS, SYSTEMS AND PROCESSES

An electronic circuit includes a receiver circuit (BSP) operable to perform coherent summations having a coherent summations time interval, and a power control circuit (2130) coupled to said receiver circuit (BSP) and operable to impress a power controlling duty cycle (TON, TOFF) on the receiver cir...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	RAMASUBRAMANIAN KARTHIK, WATERS DERIC WAYNE, RAGHUPATHY ARUN
Format:	Patent
Sprache:	eng
Schlagworte:	ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION
Online-Zugang:	Volltext bestellen
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