POWER-SAVING RECEIVER CIRCUITS, SYSTEMS AND PROCESSES

POWER-SAVING RECEIVER CIRCUITS, SYSTEMS AND PROCESSES

An electronic circuit includes a receiver circuit (BSP) operable to perform coherent summations having a coherent summations time interval, and a power control circuit (2130) coupled to said receiver circuit (BSP) and operable to impress a power controlling duty cycle (TON, TOFF) on the receiver cir...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: RAMASUBRAMANIAN KARTHIK, WATERS DERIC WAYNE, RAGHUPATHY ARUN
Format: Patent
Sprache:eng
Schlagworte:
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION
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Beschreibung
Zusammenfassung:An electronic circuit includes a receiver circuit (BSP) operable to perform coherent summations having a coherent summations time interval, and a power control circuit (2130) coupled to said receiver circuit (BSP) and operable to impress a power controlling duty cycle (TON, TOFF) on the receiver circuit (BSP) inside the coherent summations time interval. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.