Alternating Wordline Connection in 8T Cells for Improving Resiliency to Multi-Bit SER Upsets

Alternating Wordline Connection in 8T Cells for Improving Resiliency to Multi-Bit SER Upsets

An integrated circuit memory is disclosed in which an array of 8 T SRAM cells is arranged in rows and columns using a plurality of write wordlines for each row of 8 T SRAM cells to control write access to cells in the row associated with a first parity/ECC word and a second write wordline operable t...

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Bibliographische Detailangaben
Hauptverfasser: UNDERHILL KERRIE V, WEISS DON R, WUU JOHN J, WILCOX KATHRYN E, SCHAEFER ALEX W
Format: Patent
Sprache:eng
Schlagworte:
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Beschreibung
Zusammenfassung:An integrated circuit memory is disclosed in which an array of 8 T SRAM cells is arranged in rows and columns using a plurality of write wordlines for each row of 8 T SRAM cells to control write access to cells in the row associated with a first parity/ECC word and a second write wordline operable to control write access to cells in the row associated with a second parity/ECC word.