SOLDER CAP BUMP IN SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package with improved height uniformity of solder cap bumps therein is disclosed. In one embodiment, the semiconductor package includes a semiconductor substrate comprising a plurality of pads spacedly disposed on a top surface of the substrate, and a passivation layer formed on top...

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Bibliographische Detailangaben
1. Verfasser: SHEN GENG-SHIN
Format: Patent
Sprache:eng
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Zusammenfassung:A semiconductor package with improved height uniformity of solder cap bumps therein is disclosed. In one embodiment, the semiconductor package includes a semiconductor substrate comprising a plurality of pads spacedly disposed on a top surface of the substrate, and a passivation layer formed on top of the pads, wherein a plurality of pad openings are created to expose at least a portion of the pads; a plurality of solder cap bumps formed at the pad openings of the passivation layer; and a carrier substrate having a plurality of bond pads electrically connected to the solder caps of the solder cap bumps on the semiconductor substrate. The solder cap bump includes a solder cap on top of a conductive pillar, and a patternable layer can be coated and patterned on a top surface of the conductive pillar to define an area for the solder ball to be deposited. The deposited solder ball can be reflowed to form the solder cap.