SEMICONDUCTOR DEVICE

A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes first offset sidewalls formed on side surfaces in a gate width direction of a first gate electrode, second offset sidewalls formed on side surfaces in a gate length direction and the side surfaces of the gate width direction of the first gate electrode with the first offset sidewalls being interposed between the second offset sidewalls and the first gate electrode, and first extension regions. The second MIS transistor includes third offset sidewalls formed on side surfaces in a gate length direction and a gate width direction of a second gate electrode, fourth offset sidewalls formed on the side surfaces in the gate length and width directions of the second gate electrode with the third offset sidewalls being interposed between the fourth offset sidewalls and the second gate electrode, and second extension regions.