System and Method for Packaging of High-Voltage Semiconductor Devices

A method and an electronic device structure comprising at least one access lead to adapted to be connected to an electrical circuit; at least one substrate region; at least one semiconductor die positioned on the substrate; the at least one semiconductor die being operatively connected to the at least one access lead; a dielectric region extending below the at least one semiconductor die; the dielectric region being formed by creating a cavity in the at least one substrate region; whereby the dielectric region operates to reduce electric field stresses produced by the at least one semiconductor die to thereby reduce the possibility of material failure and voltage breakdown. The method of making an electronic device structure comprises providing at least one substrate region; providing at least one semiconductor die located on the at least one substrate region; removing a portion of the at least one substrate region to provide a dielectric region within the substrate extending below the at least one semiconductor die; whereby the dielectric region within the at least one substrate region operates to reduce electric field stresses produced by the at least one semiconductor die to thereby reduce the possibility of material failure and voltage breakdown.