Graphics Rendering Using A Hierarchical Acceleration Structure

A hierarchical acceleration structure may be built for graphics processing using a 32 bit format. In one embodiment, the acceleration structure may be a k-d tree, but other acceleration structures may be used as well. 64 bit offsets are only used when 64 bit offsets are needed.

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Bibliographische Detailangaben
Hauptverfasser:	RESHETOV ALEXANDER V, SOUPIKOV ALEXEI, SHEVTSOV MAXIM Y
Format:	Patent
Sprache:	eng
Schlagworte:	ADVERTISING ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION CALCULATING COMPUTING COUNTING CRYPTOGRAPHY DISPLAY EDUCATION IMAGE DATA PROCESSING OR GENERATION, IN GENERAL PHYSICS SEALS
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Beschreibung
Zusammenfassung:	A hierarchical acceleration structure may be built for graphics processing using a 32 bit format. In one embodiment, the acceleration structure may be a k-d tree, but other acceleration structures may be used as well. 64 bit offsets are only used when 64 bit offsets are needed.