Power MOSFET Having a Strained Channel in a Semiconductor Heterostructure on Metal Substrate
A method for forming a semiconductor device includes forming a graded silicon-germanium (SiGe) layer overlying a silicon substrate, a concentration of germanium increasing with a thickness of the graded silicon germanium layer. A first relaxed SiGe layer is formed over the graded SiGe layer, and a s...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | A method for forming a semiconductor device includes forming a graded silicon-germanium (SiGe) layer overlying a silicon substrate, a concentration of germanium increasing with a thickness of the graded silicon germanium layer. A first relaxed SiGe layer is formed over the graded SiGe layer, and a second relaxed SiGe layer overlying the first relaxed SiGe layer. The second relaxed SiGe layer has a lower conductivity than the first relaxed SiGe layer. The method also includes forming a field effect transistor having a trench extending into the second relaxed SiGe layer and a channel region that includes a layer of strained silicon to enable enhanced carrier mobility. A top conductor layer is formed overlying the second relaxed SiGe layer, and then the silicon substrate and the graded SiGe layer are removed. A bottom conductor layer is formed underlying the first relaxed SiGe layer. |
---|