METHOD AND APPARATUS FOR ADDRESSING AND IMPROVING HOLDS IN LOGIC NETWORKS

A method and apparatus for modifying a synchronous logic network so that the hold slack calculated at all pins is greater than or equal to a user-specified threshold, with the condition that the setup slack at any pin does not become negative or smaller than a user-specified margin. The result is an...

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Hauptverfasser: VENKATACHAR ASHOK, GONZALEZ GEORGE A, PALISETTI VASANT, HANNAN PETE J, MCGEE WILLIAM A
Format: Patent
Sprache:eng
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Zusammenfassung:A method and apparatus for modifying a synchronous logic network so that the hold slack calculated at all pins is greater than or equal to a user-specified threshold, with the condition that the setup slack at any pin does not become negative or smaller than a user-specified margin. The result is an improved design which is less likely to fail due to a hold time violation. The method and apparatus introduce a limited number of logic cells which helps keep power consumption and design size to a minimum.