METHOD AND APPARATUS FOR PROVIDING EARLY BYPASS DETECTION TO REDUCE POWER CONSUMPTION WHILE READING REGISTER FILES OF A PROCESSOR

A method and apparatus are described for reducing power consumption in a processor. A micro-operation is selected for execution, and a destination physical register tag of the selected micro-operation is compared to a plurality of source physical register tags of micro-operations dependent upon the...

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Hauptverfasser: VENKATARAMANAN GANESH, TALPES EMIL
Format: Patent
Sprache:eng
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Zusammenfassung:A method and apparatus are described for reducing power consumption in a processor. A micro-operation is selected for execution, and a destination physical register tag of the selected micro-operation is compared to a plurality of source physical register tags of micro-operations dependent upon the selected micro-operation. If there is a match between the destination physical register tag and one of the source physical register tags, a corresponding physical register file (PRF) read operation is disabled. The comparison may be performed by a wakeup content-addressable memory (CAM) of a scheduler. The wakeup CAM may send a read control signal to the PRF to disable the read operation. Disabling the corresponding PRF read operation may include shutting off power in the PRF and related logic.