CONTROLLED CONTACT FORMATION PROCESS

CONTROLLED CONTACT FORMATION PROCESS

A structure and method for replacement metal gate (RMG) field effect transistors is disclosed. Silicide regions are formed on a raised source-drain (RSD) structure. The silicide regions form a chemical mechanical polish (CMP) stopping layer during a CMP process used to expose the gates prior to repl...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: RAMACHANDRAN RAVIKUMAR, SARDESAI VIRAJ YASHAWANT, UTOMO HENRY K, LEVEDAKIS DIMITRI ANASTASSIOS, VENIGALLA RAJASEKHAR, KWON UNOH
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator RAMACHANDRAN RAVIKUMAR
SARDESAI VIRAJ YASHAWANT
UTOMO HENRY K
LEVEDAKIS DIMITRI ANASTASSIOS
VENIGALLA RAJASEKHAR
KWON UNOH
description A structure and method for replacement metal gate (RMG) field effect transistors is disclosed. Silicide regions are formed on a raised source-drain (RSD) structure. The silicide regions form a chemical mechanical polish (CMP) stopping layer during a CMP process used to expose the gates prior to replacement. Protective layers are then applied and etched in the formation of metal contacts.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2012112290A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2012112290A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2012112290A13</originalsourceid><addsrcrecordid>eNrjZFBx9vcLCfL38XF1UQAxHZ1DFNz8g3wdQzz9_RQCgvydXYODeRhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfGiwkYGhkaGhkZGlgaOhMXGqACJsJBc</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CONTROLLED CONTACT FORMATION PROCESS</title><source>esp@cenet</source><creator>RAMACHANDRAN RAVIKUMAR ; SARDESAI VIRAJ YASHAWANT ; UTOMO HENRY K ; LEVEDAKIS DIMITRI ANASTASSIOS ; VENIGALLA RAJASEKHAR ; KWON UNOH</creator><creatorcontrib>RAMACHANDRAN RAVIKUMAR ; SARDESAI VIRAJ YASHAWANT ; UTOMO HENRY K ; LEVEDAKIS DIMITRI ANASTASSIOS ; VENIGALLA RAJASEKHAR ; KWON UNOH</creatorcontrib><description>A structure and method for replacement metal gate (RMG) field effect transistors is disclosed. Silicide regions are formed on a raised source-drain (RSD) structure. The silicide regions form a chemical mechanical polish (CMP) stopping layer during a CMP process used to expose the gates prior to replacement. Protective layers are then applied and etched in the formation of metal contacts.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20120510&amp;DB=EPODOC&amp;CC=US&amp;NR=2012112290A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20120510&amp;DB=EPODOC&amp;CC=US&amp;NR=2012112290A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>RAMACHANDRAN RAVIKUMAR</creatorcontrib><creatorcontrib>SARDESAI VIRAJ YASHAWANT</creatorcontrib><creatorcontrib>UTOMO HENRY K</creatorcontrib><creatorcontrib>LEVEDAKIS DIMITRI ANASTASSIOS</creatorcontrib><creatorcontrib>VENIGALLA RAJASEKHAR</creatorcontrib><creatorcontrib>KWON UNOH</creatorcontrib><title>CONTROLLED CONTACT FORMATION PROCESS</title><description>A structure and method for replacement metal gate (RMG) field effect transistors is disclosed. Silicide regions are formed on a raised source-drain (RSD) structure. The silicide regions form a chemical mechanical polish (CMP) stopping layer during a CMP process used to expose the gates prior to replacement. Protective layers are then applied and etched in the formation of metal contacts.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFBx9vcLCfL38XF1UQAxHZ1DFNz8g3wdQzz9_RQCgvydXYODeRhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfGiwkYGhkaGhkZGlgaOhMXGqACJsJBc</recordid><startdate>20120510</startdate><enddate>20120510</enddate><creator>RAMACHANDRAN RAVIKUMAR</creator><creator>SARDESAI VIRAJ YASHAWANT</creator><creator>UTOMO HENRY K</creator><creator>LEVEDAKIS DIMITRI ANASTASSIOS</creator><creator>VENIGALLA RAJASEKHAR</creator><creator>KWON UNOH</creator><scope>EVB</scope></search><sort><creationdate>20120510</creationdate><title>CONTROLLED CONTACT FORMATION PROCESS</title><author>RAMACHANDRAN RAVIKUMAR ; SARDESAI VIRAJ YASHAWANT ; UTOMO HENRY K ; LEVEDAKIS DIMITRI ANASTASSIOS ; VENIGALLA RAJASEKHAR ; KWON UNOH</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2012112290A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>RAMACHANDRAN RAVIKUMAR</creatorcontrib><creatorcontrib>SARDESAI VIRAJ YASHAWANT</creatorcontrib><creatorcontrib>UTOMO HENRY K</creatorcontrib><creatorcontrib>LEVEDAKIS DIMITRI ANASTASSIOS</creatorcontrib><creatorcontrib>VENIGALLA RAJASEKHAR</creatorcontrib><creatorcontrib>KWON UNOH</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>RAMACHANDRAN RAVIKUMAR</au><au>SARDESAI VIRAJ YASHAWANT</au><au>UTOMO HENRY K</au><au>LEVEDAKIS DIMITRI ANASTASSIOS</au><au>VENIGALLA RAJASEKHAR</au><au>KWON UNOH</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CONTROLLED CONTACT FORMATION PROCESS</title><date>2012-05-10</date><risdate>2012</risdate><abstract>A structure and method for replacement metal gate (RMG) field effect transistors is disclosed. Silicide regions are formed on a raised source-drain (RSD) structure. The silicide regions form a chemical mechanical polish (CMP) stopping layer during a CMP process used to expose the gates prior to replacement. Protective layers are then applied and etched in the formation of metal contacts.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2012112290A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title CONTROLLED CONTACT FORMATION PROCESS
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-11T21%3A45%3A51IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=RAMACHANDRAN%20RAVIKUMAR&rft.date=2012-05-10&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2012112290A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true