CACHE MEMORY DEVICE, CACHE MEMORY CONTROL METHOD, PROGRAM AND INTEGRATED CIRCUIT

To aim to provide a cache memory device that performs a line size determination process for determining a refill size, in advance of a refill process that is performed at cache miss time. According to the line size determination process, the number of reads/writes of a management target line that belongs to a set is acquired (S51), and in the case where the numbers of reads completely match one another and the numbers of writes completely match one another (S52: Yes), the refill size is determined to be large (S54). Otherwise (S52: No), the refill size is determined to be small (S55).