STRESS MEMORIZATION PROCESS IMPROVEMENT FOR IMPROVED TECHNOLOGY PERFORMANCE

STRESS MEMORIZATION PROCESS IMPROVEMENT FOR IMPROVED TECHNOLOGY PERFORMANCE

Semiconductor substrate with a deformed gate region and a method for the fabrication thereof. The semiconductor substrate has improved device performance compared to devices without a deformed gate region and decreased dopant loss compared to devices with deformed source/drain regions.

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Bibliographische Detailangaben
Hauptverfasser: MEHTA SANJAY, DORIS BRUCE B, ADAM LAHIR SHAIK, ZHU ZHENGMAO
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:Semiconductor substrate with a deformed gate region and a method for the fabrication thereof. The semiconductor substrate has improved device performance compared to devices without a deformed gate region and decreased dopant loss compared to devices with deformed source/drain regions.