TEST SIGNAL GENERATING DEVICE, SEMICONDUCTOR MEMORY APPARATUS USING THE SAME AND MULTI-BIT TEST METHOD THEREOF
A semiconductor memory apparatus includes a multi-bit test signal generating device configured to receive an address signal and generate a multi-bit test signal based on the address signal when a multi-bit test write operation is performed.
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A semiconductor memory apparatus includes a multi-bit test signal generating device configured to receive an address signal and generate a multi-bit test signal based on the address signal when a multi-bit test write operation is performed. |
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