VERIFICATION OF PROCESSOR ARCHITECTURES ALLOWING FOR SELF MODIFYING CODE

VERIFICATION OF PROCESSOR ARCHITECTURES ALLOWING FOR SELF MODIFYING CODE

A verification operation including generating a predefined instruction, initializing a relevant self modifying code (SMC) target memory location to form an SMC trap, binding the SMC trap to the predefined instruction to form an SMC trap source and propagating initialization of instruction code into...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: RIMON MICHAL, KRYGOWSKI CHRISTOPHER A, ALMOG ELI, MORIMOTO YUGI
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A verification operation including generating a predefined instruction, initializing a relevant self modifying code (SMC) target memory location to form an SMC trap, binding the SMC trap to the predefined instruction to form an SMC trap source and propagating initialization of instruction code into the SMC trap source.