Multi-Processor

A multi-processor according to an example of the invention comprises a first control unit which stores first compressed data acquired externally in a first memory, a hardware decoding unit which decodes the first compressed data stored in the first memory and storing the decoded data in a second memory, an encoding processor element which includes at least one of a plurality of processor elements, encodes the decoded data stored in the second memory in accordance with encoding software stored in a third memory, and stores second compressed data obtained by encoding the decoded data in a fourth memory, and a second control unit which outputs the second compressed data stored in the fourth memory to the outside.