Horizontal Cache Persistence In A Multi-Compute Node, Symmetric Multiprocessing Computer

Horizontal cache persistence in a multi-compute node, SMP computer, including, responsive to a determination to evict a cache line on a first one of the compute nodes, broadcasting by a first compute node an eviction notice for the cache line; transmitting the state of the cache line receiving compute nodes, including, if the cache line is missing from a compute node, an indication whether that compute node has cache storage space available for the cache line; determining by the first compute node, according to the states of the cache line and space available, whether the first compute node can evict the cache line without writing the cache line to main memory; and updating by each compute node the state of the cache line in each compute node, in dependence upon one or more of the states of the cache line in all the compute nodes.