Method For Wafer Level Package and Semiconductor Device Fabricated Using The Same

Method For Wafer Level Package and Semiconductor Device Fabricated Using The Same

Provided is a wafer level packaging method and a semiconductor device fabricated using the same. In the method, a substrate comprising a plurality of chips is provided. An adhesive layer is formed on the substrate corresponding to boundaries of the plurality of chips. A cover plate covering an upper...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: JANG HYUNG-SUN, KANG UN-BYOUNG, CHO TAEJE, LEE HYUEKJAE, HONG JISUN, KIM YOUNGBOK
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:Provided is a wafer level packaging method and a semiconductor device fabricated using the same. In the method, a substrate comprising a plurality of chips is provided. An adhesive layer is formed on the substrate corresponding to boundaries of the plurality of chips. A cover plate covering an upper portion of the substrate and having at least one opening exposing the adhesive layer or the substrate at the boundaries among the plurality of chips is attached to the adhesive layer.