GAIN NORMALIZATION OF A TIME-TO-DIGITAL CONVERTER

The invention relates to normalisation of a TDC system (20). The TDC system (20) comprises a TDC core (21), a gain normalization circuit (22) and an adjuster (23). The TDC core (21) comprises a set of nominally identical delay elements and converts the time difference between the edges of a reference clock signal (FREF) and a controllable clock signal (CLK) into a raw TDC output code as a digital word. The adjuster (23) is configured to carry out the gain normalisation by adjusting the output code. The gain normalization circuit (22) comprises at least a processor for analyzing the occurrence probability of the output code values, and for determining the adjustment to be made by the adjuster (23) according to said occurrence probability.