METHOD OF GENERATING MASK PATTERN, MASK PATTERN GENERATING PROGRAM, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

METHOD OF GENERATING MASK PATTERN, MASK PATTERN GENERATING PROGRAM, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

According to one embodiment, in process simulation, it is verified whether sidewall patterns formed on sidewalls of a core material pattern or a transfer pattern formed by transferring the core material pattern form a closed loop. When it is determined as a result of the verification that the sidewa...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: KOTANI TOSHIYA, ABURADA RYOTA
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:According to one embodiment, in process simulation, it is verified whether sidewall patterns formed on sidewalls of a core material pattern or a transfer pattern formed by transferring the core material pattern form a closed loop. When it is determined as a result of the verification that the sidewall patterns form a closed loop, the mask pattern is changed. When it is determined as a result of the verification that the sidewall patterns do not form a closed loop, the mask pattern is adopted.