MASSIVELY PARALLEL, SMART MEMORY BASED ACCELERATOR

MASSIVELY PARALLEL, SMART MEMORY BASED ACCELERATOR

Systems and methods for massively parallel processing on an accelerator that includes a plurality of processing cores. Each processing core includes multiple processing chains configured to perform parallel computations, each of which includes a plurality of interconnected processing elements. The c...

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Bibliographische Detailangaben
Hauptverfasser: BECCHI MICHELA, CADAMBI SRIHARI, MAJUMDAR ABHINANDAN, CHAKRADHAR SRIMAT, GRAF HANS PETER
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:Systems and methods for massively parallel processing on an accelerator that includes a plurality of processing cores. Each processing core includes multiple processing chains configured to perform parallel computations, each of which includes a plurality of interconnected processing elements. The cores further include multiple of smart memory blocks configured to store and process data, each memory block accepting the output of one of the plurality of processing chains. The cores communicate with at least one off-chip memory bank.