TIERED SCHEMATIC-DRIVEN LAYOUT SYNCHRONIZATION IN ELECTRONIC DESIGN AUTOMATION

Some embodiments provide a system that facilitates the creation of a layout from a schematic in an electronic design automation (EDA) application. During operation, the system performs a tiered comparison of the schematic and the layout. The tiered comparison includes a first tier that compares labe...

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Bibliographische Detailangaben
Hauptverfasser: SUN WERN-JIEH, MAYER ERNST W, CHUN HAICHUN, WOOLHISER GREG, KARLCUT KULDEEP
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:Some embodiments provide a system that facilitates the creation of a layout from a schematic in an electronic design automation (EDA) application. During operation, the system performs a tiered comparison of the schematic and the layout. The tiered comparison includes a first tier that compares labels in the schematic and the layout. The tiered comparison also includes a second tier that compares first-level connectivity in the schematic and the layout. The tiered comparison further includes a third tier that determines a graph isomorphism between the schematic and the layout. After the tiered comparison is completed, the system provides a result of the tiered comparison to a user of the EDA application. Finally, the system enables repairs of mismatches in the result by the user through a graphical user interface (GUI) associated with the EDA application.