Circuit arrangement, systems for transmitting a serial data stream, pixel matrix display and method for transmitting a serial data stream

A circuit arrangement comprises an input circuit for reading in a serial data stream, which comprises a plurality of useful data bits, and for reading in a piece of information which indicates the start of the serial data stream. The circuit arrangement also comprises a data processing circuit for removing at least one useful data bit from the read-in, serial data stream. The data processing circuit is designed such that it removes the at least one useful data bit at a prescribed position after the start of the serial data stream. The circuit arrangement also comprises a first output circuit for outputting the read-in, serial data stream for the omission of the at least one removed useful data bit.