METHOD FOR FORMING BIT LINES FOR SEMICONDUCTOR DEVICES

METHOD FOR FORMING BIT LINES FOR SEMICONDUCTOR DEVICES

A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may in...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: RAMSBEY MARK T, KAMAL TAZRIEN, QIAN WEIDONG
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator RAMSBEY MARK T
KAMAL TAZRIEN
QIAN WEIDONG
description A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity,
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2010330762A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2010330762A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2010330762A13</originalsourceid><addsrcrecordid>eNrjZDDzdQ3x8HdRcPMPAmFfTz93BSfPEAUfTz_XYLBosKuvp7O_n0uocwiQ5-Ia5unsGszDwJqWmFOcyguluRmU3VxDnD10Uwvy41OLCxKTU_NSS-JDg40MDA2MjQ3MzYwcDY2JUwUAqMUovg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD FOR FORMING BIT LINES FOR SEMICONDUCTOR DEVICES</title><source>esp@cenet</source><creator>RAMSBEY MARK T ; KAMAL TAZRIEN ; QIAN WEIDONG</creator><creatorcontrib>RAMSBEY MARK T ; KAMAL TAZRIEN ; QIAN WEIDONG</creatorcontrib><description>A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity,</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20101230&amp;DB=EPODOC&amp;CC=US&amp;NR=2010330762A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20101230&amp;DB=EPODOC&amp;CC=US&amp;NR=2010330762A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>RAMSBEY MARK T</creatorcontrib><creatorcontrib>KAMAL TAZRIEN</creatorcontrib><creatorcontrib>QIAN WEIDONG</creatorcontrib><title>METHOD FOR FORMING BIT LINES FOR SEMICONDUCTOR DEVICES</title><description>A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity,</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDzdQ3x8HdRcPMPAmFfTz93BSfPEAUfTz_XYLBosKuvp7O_n0uocwiQ5-Ia5unsGszDwJqWmFOcyguluRmU3VxDnD10Uwvy41OLCxKTU_NSS-JDg40MDA2MjQ3MzYwcDY2JUwUAqMUovg</recordid><startdate>20101230</startdate><enddate>20101230</enddate><creator>RAMSBEY MARK T</creator><creator>KAMAL TAZRIEN</creator><creator>QIAN WEIDONG</creator><scope>EVB</scope></search><sort><creationdate>20101230</creationdate><title>METHOD FOR FORMING BIT LINES FOR SEMICONDUCTOR DEVICES</title><author>RAMSBEY MARK T ; KAMAL TAZRIEN ; QIAN WEIDONG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2010330762A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>RAMSBEY MARK T</creatorcontrib><creatorcontrib>KAMAL TAZRIEN</creatorcontrib><creatorcontrib>QIAN WEIDONG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>RAMSBEY MARK T</au><au>KAMAL TAZRIEN</au><au>QIAN WEIDONG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD FOR FORMING BIT LINES FOR SEMICONDUCTOR DEVICES</title><date>2010-12-30</date><risdate>2010</risdate><abstract>A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity,</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2010330762A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title METHOD FOR FORMING BIT LINES FOR SEMICONDUCTOR DEVICES
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-26T15%3A02%3A54IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=RAMSBEY%20MARK%20T&rft.date=2010-12-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2010330762A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true