CAPACITOR AND A METHOD OF MANUFACTURING A CAPACITOR

A device comprises a substrate (22); a first MiM capacitor (10,20,11) disposed over the substrate; and a second MiM capacitor (10′,20′,11) disposed over the first MiM capacitor. The first MiM capacitor and the second MiM capacitor are electrically connected in parallel. The two MiM capacitors are vertically stacked one above the other. Each MiM capacitor comprises an interconnection layer (10,10′) of the CMOS process as one plate and a thinner conductive layer (11,11′) as the second plate, with an insulating layer (20,20′) disposed therebetween. This allows each MiM capacitor to be formed between two CMOS process interconnection layers. The second plate of the second MiM capacitor is substantially co-extensive with the second plate of the first MiM capacitor, and is disposed substantially directly over the second plate of the first MiM capacitor. The same mask may be used to pattern the second plate of the second MiM capacitor and the second plate of the first MiM capacitor. This minimises the number of masks required, and so minimises the mask investment cost.